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GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver
May 1999 Revised September 1999
GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver
General Description
The GTLP18T612 is an 18-bit universal bus transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP's reduced output swing (< 1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3. Fairchild's GTLP has internal edge-rate control and is Process, Voltage, and Temperature (PVT) compensated. Its function is similar to BTL or GTL but with different output levels and receiver thresholds. GTLP output LOW level is less than 0.5V, the output HIGH is 1.5V and the receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and LVTTL logic levels s Edge Rate Control to minimize noise on the GTLP port s Power up/down high impedance for live insertion s External VREF pin for receiver threshold s BiCMOS technology for low power dissipation s Bushold data inputs on A Port eliminates the need for external pull-up resistors for unused inputs s LVTTL compatible Driver and Control inputs s Flow-through architecture optimizes PCB layout s Open drain on GTLP to support wired-or connection s A-Port source/sink -24 mA/+24 mA s B-Port sink capability +50 mA s D-type flip-flop, latch and transparent data paths
Ordering Code:
Order Number GTLP18T612MEA GTLP18T612MTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
(c) 1999 Fairchild Semiconductor Corporation
DS500169
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GTLP18T612
Pin Descriptions
Pin Names Description OEAB OEBA CEAB CEBA LEAB LEBA VREF CLKAB CLKBA A1-A18 B1-B18 A-to-B Output Enable (Active LOW) (LVTTL Level) B-to-A Output Enable (Active LOW) (LVTTL Level) A-to-B Clock/LE Enable (Active LOW) (LVTTL Level) B-to-A Clock/LE Enable (Active LOW) (LVTTL Level) A-to-B Latch Enable (Transparent HIGH) (LVTTL Level) B-to-A Latch Enable (Transparent HIGH) (LVTTL Level) GTLP Input Threshold Reference Voltage A-to-B Clock (LVTTL Level) B-to-A Clock (LVTTL Level) A-to-B Data Inputs or B-to-A 3-STATE Outputs B-to-A Data Inputs or A-to-B Open Drain Outputs
Connection Diagram
Functional Description
The GTLP18T612 is an 18 bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation for the data path. Data flow in each direction is controlled by the clock enables (CEAB and CEBA), latch enables (LEAB and LEBA), clock (CLKAB and CLKBA) and output enables (OEAB and OEBA). The clock enables (CEAB and CEBA) and the output enables (OEAB and OEBA) control the 18 bits of data for the A-to-B and B-to-A directions respectively. For A-to-B data flow, when CEAB is LOW, the device operates on the LOW-to-HIGH transition of CLKAB for the flip-flop and on the HIGH-to-LOW transition of LEAB for the latch path. That is, if CEAB is LOW and LEAB is LOW the A data is latched regardless as to the state of CLKAB (HIGH or LOW) and if LEAB is HIGH the device is in transparent mode. When OEAB is LOW the outputs are active. When OEAB is HIGH the outputs are HIGH impedance. The data flow of B-to-A is similar except that CEBA, OEBA, LEBA, and CLKBA are used.
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GTLP18T612
Truth Table (Note 1)
Inputs CEAB X L L X X L L OEAB H L L L L L L LEAB X L L H H L L CLKAB X H or L H or L X X A X X X L H L H Z B0 (Note 2) B0 (Note 3) L H L H Clocked storage of A data H L L X X B0 (Note 3) Clock inhibit Latched storage of A data Transparent Output B Mode
Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA. Note 2: Output level before the indicated steady state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. Note 3: Output level before the indicated steady-state input conditions were established.
Logic Diagram
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GTLP18T612
Absolute Maximum Ratings(Note 4)
Supply Voltage (VCC ) DC Input Voltage (VI) DC Output Voltage (VO) Outputs 3-STATE Outputs Active (Note 5) DC Output Sink Current into A Port IOL DC Output Source Current from A Port IOH DC Output Sink Current into B Port in the LOW State, IOL DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V VO > VCC ESD Performance Storage Temperature (TSTG) -50 mA +50 mA >2000V -65C to +150C -50 mA 100 mA -48 mA 48 mA -0.5V to +4.6V -0.5V to VCC + 0.5V -0.5V to +4.6V -0.5V to +4.6V
Recommended Operating Conditions (Note 6)
Supply Voltage VCC /VCCQ Bus Termination Voltage (VTT) GTLP VREF Input Voltage (VI) on A Port and Control Pins on B Port HIGH Level Output Current (IOH) A Port LOW Level Output Current (IOL) A Port B Port Operating Temperature (TA) +24 mA +50 mA -40C to +85C -24 mA 0.0V to 3.45V 0.0V to 3.45V 1.47V to 1.53V 0.98V to 1.02V 3.15V to 3.45V
Note 4: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions in not implied. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Unused inputs must be held HIGH or LOW.
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted). Symbol VIH VIL VREF VIK VOH A Port B Port Others B Port Others GTLP (Note 8) GTL VCC = 3.15V VCC, VCCQ = Min to Max (Note 9) VCC = 3.15V VOL A Port B Port II Control Pins A Port B Port IOFF II(hold) IOZH IOZL VCC, VCCQ = Min to Max (Note 9) VCC = 3.15V VCC = 3.15V VCC = Min to Max (Note 9) VCC = 3.45V VCC = 3.45V II = -18 mA IOH = -100 A IOH = -8 mA IOH = -24mA IOL = 100 A IOL = 24mA IOL = 40 mA IOL = 50 mA VI = 3.45V or 0V VI = 0V VI = 3.45 VI = VCC VI = 0 A Port and Control Pins VCC = 0 A Port A Port B Port A Port B Port VCC = 3.45V VCC = 3.15V VCC = 3.45V VI or VO = 0 to 3.45V VI = 0.8V VI = 2.0V VO = 3.45 VO = 1.5V VO = 0V VO = 0.55V 75 -75 10 5 -10 -5 VCC -0.2 2.4 2.0 0.2 0.5 0.40 0.55 5 -10 10 5 -5 30 V V A A A A A A A V 1.0 0.8 -1.2 Test Conditions Min VREF +0.05 2.0 0.0 VREF - 0.05 0.8 Typ (Note 7) Max VTT Units V V V V
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GTLP18T612
DC Electrical Characteristics
Symbol ICC (VCC/VCCQ) ICC (Note 10) Ci A Port and Control Pins Control Pins A Port B Port A or B Ports VCC = 3.45V IO = 0 VI = VCC or GND VCC = 3.45V,
(Continued)
Typ (Note 7) 30 30 30 0 6 7.5 9.0 pF
Test Conditions Outputs HIGH Outputs LOW Outputs Disabled One Input at 2.7V VI = VCC or 0 VI = VCC or 0 VI = VCC or 0
Min
Max 40 40 45 2
Units
mA mA
A or Control Inputs at VCC or GND
Note 7: All typical values are at VCC = 3.3V, VCCQ = 3.3V, and TA = 25C. Note 8: GTLP VREF and VTT are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy. In addition, VTT and Rterm can be adjusted beyond the recommended operating conditions to accommodate backplane impedances other than 50, but must remain within the boundaries of the DC Absolute Maximum ratings. Similarly VREF can be adjusted to optimize noise margin. Note 9: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. Note 10: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
AC Operating Requirements
Over recommended ranges of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted). Symbol fCLOCK tWIDTH tSU Maximum Clock Frequency Pulse Duration Setup Time LEAB or LEBA HIGH CLKAB or CLKBA HIGH or LOW A before CLKAB B before CLKBA A before LEAB B before LEBA CEAB before CLKAB CEBA before CLKBA tHOLD Hold Time A after CLKAB B after CLKBA A after LEAB B after LEBA CEAB after CLKAB CEBA after CLKBA Test Conditions Min 0 3.0 3.0 1.1 3.0 1.1 2.7 1.2 1.4 0.0 0.0 0.8 0.0 1.0 1.9 ns ns Max 175 Unit MHz ns
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GTLP18T612
AC Electrical Characteristics
Over recommended range of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted).
CL = 30 pF for B Port and CL = 50 pF for A Port.
Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tRISE tFALL tPLH tPHL tPLH tPHL tPLH tPHL tPZH, tPZL tPHZ, tPLZ
Note 11: All typical values are at VCC = 3.3V, and TA = 25C.
From (Input) A LEAB CLKAB
To (Output) B B B
Min 2.1 1.0 2.2 1.0 2.2 1.0
Typ (Note 11) 4.1 2.7 4.2 2.4 4.4 2.5 3.8 2.6 3.1 2.1
Max 6.3 4.4 6.3 4.2 6.5 4.4 5.6 4.3
Unit ns ns ns
OEAB
B
2.0 1.0
ns ns
Transition time, B outputs (20% to 80%) Transition time, B outputs (20% to 80%) B LEBA CLKBA A A A 1.8 1.8 0.3 0.4 0.5 0.6 OEBA A 0.3 0.3
3.8 3.8 2.2 2.4 2.4 2.6 2.7 2.5
5.8 5.8 4.6 4.6 4.6 4.6 5.2 5.2
ns ns ns
ns
Extended Electrical Characteristics
Over recommended ranges of supply voltage and operating free-air temperature VREF = 1.0V (unless otherwise noted). CL = 30 pF for B Port and CL = 50 pF for A Port.
Symbol tOSLH (Note 12) tOSHL (Note 12) tPV(HL) (Note 13)(Note 14) tOSLH (Note 12) tOSHL (Note 12) tPV(HL) (Note 13)(Note 14) tOSLH (Note 12) tOSHL (Note 12) tOST (Note 12) tPV (Note 13) tOSLH (Note 12) tOSHL (Note 12) tOST (Note 12) tPV (Note 13) CLKAB CLKAB A A B B CLKAB A A A 0.5 0.6 1.1 CLKAB B B A 0.7 0.6 0.7 A CLKAB B B 0.9 0.3 From (Input) A To (Output) B Min Typ (Note 11) 0.8 0.3 Max 1.0 0.5 0.8 1.0 0.5 0.8 1.0 1.0 1.1 1.5 1.0 1.0 1.2 1.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 12: tOSHL/tOSLH and tOST - Output to output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs within the same packaged device. The specifications are given for specific worst case VCC and temperature and apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH) or in opposite directions both HL and LH (tOST). This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device. Note 13: tPV - Part to part skew is defined as the absolute value of the difference between the actual propagation delay for all outputs from device to device. The parameter is specified for a specific worst case VCC and temperature. This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device. Note 14: Due to the open drain structure on GTLP outputs tOST and t PV(LH) in the A-to-B direction are not specified. Skew on these paths is dependent on the VTT and RT values on the backplane.
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GTLP18T612
Test Circuits and Timing Waveforms
Test Circuit for A Outputs Test Circuit for B Outputs
Test tPLZ/tPZL
S 6V
Note B: For B Port, CL = 30 pF is used for worst case.
tPLH/tPHL Open tPHZ/tPZH GND
Note A: CL includes probes and Jig capacitance.
Voltage Waveform - Propagation Delay Times
Voltage Waveform - Setup and Hold Times
Voltage Waveform - Pulse Width
Voltage Waveform - Enable and Disable times
Output Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the control output. Output Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the control output.
Input and Measure Conditions A or LVTTL Pins VinHIGH VinLOW VM VX VY 3.0 0.0 1.5 VOL + 0.3V VOH - 0.3V B or GTLP Pins 1.5 0.0 1.0 N/A N/A
All input pulses have the following characteristics: Frequency = 10MHz, tRISE = tFALL = 2 ns (10% to 90%), Z O = 50. The outputs are measured one at a time with one transition per measurement.
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GTLP18T612
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS56A
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GTLP18T612 18-Bit LVTTL/GTLP Universal Bus Transceiver
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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